引言
本文在上一讲逐渐熟悉了VCS的开关选项后，下面继续介绍VCS的使用，我始终关注于熟悉工具的使用，在本系列中，对Verilog的语法不作深入研究，这样可以加快前进的步伐。也为了加快从FPGA中转变到IC领域来。在本文中将介绍VCS 调试基础。
1、基础理论讲义
—Afer completing this unit ,you should be able to:
- Describe three methods of debugging Verilog code using VCS
- Invoke UCLI debugger
- Debug Verilog designs using UCLI
–VCS Debugging Suport
4. Trance and locate causes of errors
5. Three general debugging methods:
-
Verilog SystemVerilog System Task calls
VCS UCLI
VCS DVE(GUI) -
Four factors to consider:
simulation speed
signal visibility
sgnal tractability
usability
Verilog System Task For Debugging 利用verilog的系统函数
- Debug visibility:
- $ display prints formatted message to console
- $ strobe Like$dispaly except printing is delayed until all events in the current time step have executed
- $ monitor Monitor signals listed and prints formatted message whenever one of the listed signals changes
- $ time returns current simulation time as a 64bits integer
-
Stopping simulations:
$stop halts simulation lie a breakpoint
$finish halts simulation and terminated the simulation session -
Simulation stimulus and reference:
- r e a d m e m h R e a d s A S C I I d a t a f r o m a d i s k f i l e , e a c h d i g i t i s h e x a d e c i m a l − readmemh Reads ASCII data from a disk file,each digit is hexadecimal - rea
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