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SPU LLVM: Support PUTLLC16 in CellSpurs JobChain management - #17733
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elad335
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Hi do you need any types of tests? Also can you marge master to it as there are also new optimizations so it will be hard to compare speed without them here? |
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Yes you can test performamce differences. |
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God of war 3 difference is too small so probably difference in gameplay. In Uncharted 1 I saw difference between 76.5 max (master) and 68..5 on branch but it can be because of gameplay or something. All other stats are similar: |
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The branch crashes resistance 3. The crash can be reproduced in the "Haven" demo as well. |
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Resistance 3 is fixed! |
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I made some testing and apparently I didn't get crashes or regressions. On my games, I didn't see performance improvement but probably they are not affected by this changes |
Experimental, may be reduced to specific patterns instead of being enabled globally.
_aligned_realloc may return the same pointer if the internal implementation finds it suitable. Fixes Windows' builds.
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This change (RPCS3 build 18413) crashes Ratchet & Clank - Into the Nexus, planet Igliak, immediately when you swingshot across the opening swingshot targets ("SIG: Thread terminated due to fatal error: PPU Trap! Sometimes tweaking the setting "Stub PPU Traps" can be a workaround to this crash."): 
Here is the relevant RPCS3 log excerpt: I know that "Into the Nexus" has random freezes, but RPCS3 builds prior to versions including this PR work fine here. This crash is 100% reproducible every time. I also looked everywhere and can't seem to find an option "Stub PPU Traps" in RPCS3 to give that a try... |
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Because this change is merged into master can you open a regression ticket following all the information that the template requests. |
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Any issues stemming from this need to go into a new regression ticket, following the template with log file, otherwise they will be missed |
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Done, thanks! |
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In Hot Shots Golf, one SPU atomic operation stands out more than the rest:
This operation, manages acquireship of cellSpurs Jobchain tasks.
After some observation, I've noticed that this atomic operation may be compatible with the PUTLLC16 optimization, which you can learn about here: #15429
But why it wasn't yet compatible for it? for few reasons it turns out.
BRSL, in the middle of the operation. But after inspecting what it does, it does not seem to make sense for the function. But after second inspection, I noticed that register 4 (R4) was used right after the function call. So I figured, that this must be a [[noreturn]] type of function which does not actually return to function. Implementing detection of this eliminates optimization failure number 1 for SPU Mega block size.After inspection, the second address cannot be interleaved with the cache line data of the operation. But, because of the usage of relative loads and stores, a runtime check was added in LLVM code to verify it. (otherwise resorting to the full and heavy PUTLLC)
Fixes #14724
Note: This pull requests affect both SPU Safe and SPU Mega block sizes.
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